Embodiments of the present invention relate generally to a system and method corresponding to part of a physical layer (PHY) in a high-speed digital communications system, and more particularly to integrating many of the physical layer functions in a high-speed digital transceiver module.
High-speed digital communication networks over copper and optical fiber are used in many network communication and digital storage applications. Ethernet and Fibre Channel are two widely used communication protocols used today and continue to evolve to respond to the increasing need for higher bandwidth in digital communication systems.
The Open Systems Interconnection (OSI) model (ISO standard) was developed to establish standardization for linking heterogeneous computer and communication systems. The OSI model includes seven distinct functional layers including Layer 7: an application layer; Layer 6: a presentation layer; Layer 5: a session layer; Layer 4: a transport layer; Layer 3: a network layer; Layer 2: a data link layer; and Layer 1: a physical layer. Each OSI layer is responsible for establishing what is to be done at that layer of the network but not how to implement it.
Layers 1 to 4 handle network control and data transmission and reception. Layers 5 to 7 handle application issues. Specific functions of each layer may vary to a certain extent, depending on the exact requirements of a given protocol to be implemented for the layer. For example, the Ethernet protocol provides collision detection and carrier sensing in the data link layer.
The physical layer, Layer 1, is responsible for handling all electrical, optical, and mechanical requirements for interfacing to the communication media. The physical layer provides encoding and decoding, synchronization, clock data recovery, and transmission and reception of bit streams. Typically, high-speed electrical or optical transceivers are the hardware elements used to implement this layer.
As data rate and bandwidth requirements increase, 10 Gigabit data transmission rates are being developed and implemented in high-speed networks. There is much pressure to develop a 10 Gigabit physical layer for high-speed serial data applications. XENPAK (XAUI module specification) compatible transceivers for 10 G applications may be used for the 10 G physical layer. XPAK (second generation to XENPAK specification) compatible transceivers for 10 G applications may also be used for the 10 G physical layer. The specification IEEE P802.3ae draft 5 describes the physical layer requirements for 10 Gigabit Ethernet applications and is incorporated herein by reference in its entirety. The 10 Gigabit Fibre Channel standard draft describes the physical layer requirements for 10 Gigabit Fibre Channel applications.
An optical-based transceiver, for example, includes various functional components such as clock data recovery, clock multiplication, serialization/de-serialization, encoding/decoding, electrical/optical conversion, descrambling, media access control, controlling, and data storage. Many of the functional components are often implemented in separate IC chips.
In the physical layer, several sublayers are supported. As an example, for 10 Gigabit serial operation, some of the key sublayers include a PMD TX/RX (physical media dependent transmit and receive) sublayer, a PMD PCS (physical media dependent physical encoding) sublayer, a XGXS PCS (10 Gigabit media independent interface extender physical encoding) sublayer, and a XAUI TX/RX (10 Gigabit attachment unit interface transmit and receive) sublayer.
FIGS. 1-3 show typical implementations of the various sublayers. In FIG. 1, the XAUI TX/RX sublayer and the XGXS PCS sublayer are implemented in CMOS on a single chip. The PMD PCS sublayer and PMD TX/RX sublayer are implemented on a second chip where the PMD PCS sublayer is implemented in 0.18 micron CMOS technology and the PMD TX/RX sublayer is implemented in SiGe technology. An interface between the two chips is required such as a XGMII (10 Gb media independent interface). The different technologies of the different chips and within the second chip require different voltage levels and, therefore, additional level translation circuitry within the transceiver module and/or within the second chip. Also, the interface between the two chips adds additional complexity and extra power dissipation to the transceiver module.
In FIG. 2, the XAUI TX/RX sublayer and the XGXS PCS and PMD PCS sublayers are implemented on a single chip in CMOS technology. The PMD TX/RX sublayer is implemented on a second chip in SiGe technology. An interface between the two chips is required. The different technologies of the different chips require different voltage levels and, therefore, additional level translation circuitry within the transceiver module. Also, the interface between the two chips adds additional complexity and extra power dissipation to the transceiver module.
In FIG. 3, the XAUI TX/RX sublayer, and the XGXS PCS and PMD PCS sublayers are implemented on a single chip in 0.18 micron CMOS technology. Also, the PMD TX/RX sublayer is implemented on the same chip with SiGe technology. All four sublayers are implemented on a single chip but using a combination of different technologies. The different technologies require different voltage levels and, therefore, additional circuitry to perform level translation of voltages within the chip. Also, the mixture of different process technologies will add extra steps to the fabrication process which will increase cost.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.